1、题目
This is the third component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.
As part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. We handle sequence detection in Exams/review2015_fsmseq, so this portion of the FSM only handles enabling the shift register for 4 cycles.
Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).
2、分析
说实话，我不太理解这个题目，觉得题目和所给的时序对不上，根据题目“Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset).”，我会以为是复位开始的四个周期为高，看了网上其它答案，才发现原来是：复位有效，使能shift_ena为高，复位无效后，使能shift_ena为高四个时钟周期，之后如果复位还是无效，那么shift_ena将保持为0
3、代码
module top_module ( input clk, input reset, output reg shift_ena ); reg [1:0] cnt; always @(posedge clk) begin if(reset) begin cnt <= 2'b00; shift_ena <= 1'b1; end else if(cnt == 2'd3) begin shift_ena <= 1'b0; cnt <= cnt; end else begin shift_ena <= 1'b1; cnt <= cnt + 1'b1; end end endmodule
